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Latest Updates

Happy New Year

Sep 07, 2018

שנה טובה
To all our dear friends, celebrating the beginning of the upcoming new year, שנה טובה,
Have a prosperous year, full of success and happiness.

Cogita Latest Release

Aug 15, 2018

We are proud to launch our newest update.
Version 3.1.1 is now available with a host of new features:

  • The quickest way to perform Root-cause-analysis using simulation log file visualization.
  • Supports all log text file.
    UVM/Specman simulation logs, LAB equipment, HW accelerators, CSV files, etc..
  • Display wave files in sync with the log files.
    VCD, TRN, VPD, FSDB
  • Support for visualizing enumerated type.
  • It is now possible to run Cogita over SSH.
  • Major speed, performance, and stability improvements.

Find out more about Cogita here.

Cogita Case Study

Aug 06, 2018

We have released a Cogita Case Study.

Watch a short hands-on case study demonstrating how Cogita was used to debug a failing test and find a bug, which would have been difficult to detect otherwise.

The DUT (Device Under Test) in question is a complex memory traffic manager that receives command packets over a proprietary bus protocol, somewhat similar to AXI.

New Belgrade Office

Jul 23, 2018

Looking for us?

Our Belgrade office has moved to a new location - Tadeuša Košćuška 18, 2nd floor.

Vtool Internship program

Jun 21, 2018
We are very pleased to announce Vtool Internship program 2018!
At Vtool, you will learn state of the art chip design, innovative practices and work methods, but more importantly, you will be part of the team that redefines them. 
Apply by sending your CV to jobs@thevtool.com  

Vtool Nominates A New Chairman Of The Board

May 21, 2018

Vtool names Dr. Nathan Zommer as the company's new Chairman of the Board.

Read full press release

Vtool at ChipEx 2018 summary

May 03, 2018

Another conference is behind us!

We had a great time at ChipEx 2018 - the largest international event of the Israeli microelectronics industry.

Hagai Arbel, the CEO of Vtool, held a presentation named: ‘’Upgrading your debug process with visual analysis’’ and presented Cogita, our ultimate tool for data screening, processing, and visualization.

 

Vtool at DVCon China 2018 summary

Apr 23, 2018

We had an amazing time at DVCon China 2018! Thank you Shanghai for hosting.
This past week Vtool took part in DVCon China 2018, the biggest and most important event in Asia covering the field of functional design and verification. Hagai Arbel and Dan Alexander held an exciting presentation based on a paper written by Anna M. Ravitzki named: “The Big Data Revolution: Beautiful Servant or Dangerous Monster?’’
If you weren’t here, have no fear, you too can experience the future of verification - with Cogita, the ultimate tool for data screening, processing, and visualization.

Vtool at DVCon China 2018!

Apr 15, 2018

The Big Data Revolution: Beautiful Servant or Dangerous Monster?

Humanity is shifting the hegemony from science onto data. At Vtool, we continuously strive to reach a state where our minds do not explode from the excess of information particles that engulf us all, which the mind cannot contain. Vtool focuses on creating measuring perceptions that maintain the power of human consciousness.

Join us at DVCon China 2018 for the presentation!

Vtool at DVCon US 2018 summary

Mar 05, 2018

Congratulations to our guys for their presentations at this year's DVCon US:

Djuro Grubor - Verification Strategy for Pipeline Type of Design
Djuro showed how is it possible to create modular verification environment to correlate with design, incorporating an advanced UVM approach. As part of this presentation, it was shown how component synchronization and communication can be established using UVM TLM elements.

Darko Tomusilovic - UVM Verification Environment Based on Software Design Patterns
Darko had a presentation concerning software design patterns. Software design pattern is a technique utilized to tackle a commonly occurring problem in the software development. As a significant part of work done by verification engineers includes coding in an object-oriented language, such as SystemVerilog, many of the encountered challenges are suitable to be resolved applying certain design patterns. Their incorporation into the code provides many benefits, contributing to the code reusability and maintainability, and therefore improving the overall code quality.

 

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