In Vtool we created a social, intelligent, ideological team that aims to find the dialogue and the inner-intellectual content that conspires with the technological life.
Technology becomes a tool that’s meant to serve authentic moments, in order to achieve an existential life. We offer articles written by our team for download.
In this case study, Cogita was used to debug a failing test and find a bug, which would have been difficult to detect otherwise.
The DUT (Device Under Test) in question is a complex memory traffic manager that receives command packets over a proprietary bus protocol, somewhat similar to AXI.
A massive-random test failed, and as usually happens in UVM based verification, the root-cause is unknown at this time. There could be a DUT bug, a scoreboard issue, a test problem of illegal scenarios…Without Cogita, the engineer would have to conduct the debug process by searching the log for meaningful information at each of the debug steps.
Humanity is shifting the hegemony from science onto data. At Vtool, we continuously strive to reach a state where our minds do not explode from the excess of information particles that engulf us all, which the mind cannot contain. Vtool focuses on creating measuring perceptions that maintain the power of human consciousness.
Join us at DVCon China 2018 for the presentation.
What is between technology and ethics?
The ethical dilemma is created by the user’s addiction to computer hours, and much like any addiction it creates a type of alienation, through the media. We each build a world of “I” for ourselves through technology, while technology itself is incapable of touching our psyche, and a complex relationship is forged between human and media.
We become the creators of content, in which language and speech exist within this mythical space – a space where the dia-log and the multi-log become an a-log-arithm that produce this existentialism in which we live. We ask to create states of dialogs, where the medium takes active part.
Software design pattern is a software development technique representing a solution to a typical problem repeatedly found over a development cycle.
This paper shows how State, Singleton, Mediator, and Template method design patterns can be utilized to efficiently model Finite - State Machines in the Verification environment. The proposed implementation improves code readability and reusability on both active generation side and passive checking and coverage collection side. It also facilitates the maintainability, by localizing the change s upon the addition of new FSM states.
The paper was presented at DVCon Europe 2017.