Visually create what you can, and code only what you need, in a two-way process that synchronizes GUI with UVM code.
Machina automatically maintains a fully documented and beautifully structured code, ensuring clear readability and high reusability.
Let Machina handle UVM complexity and integration, while you focus on the real work of core verification.
Use Machina’s simple graphical interface to create a new project or upload an existing one, and just add the properties you need (signals, fields, register files, agents, etc.), and, where required, manually code them on Vtool’s code editor (or an external editor of your preference).
Machina generates an optimized code form all your visual-based commands, automatically handling all SystemVerilog and UVM requirements (constructors, macros, etc.), while it prepares an HTML document that describes your project content.
As you add more and more functionality to your project, Machina alerts of any syntax errors, and at any point in time you can compile and run tests with a click of a button, verifying the testbench and DUT functionality.
Instead of using a code editor and a set of documents, you simply drag-and-drop the components you want onto Machina’s drawing board, selecting from a vast library of UVCs and embedded verification functions. It configures block properties, integrates the environment, and connects it to the DUT by applying an auto-assisted mechanism.
Based on a built-in SystemVerilog parser, Machina’s underlying engines quickly and automatically build the entire UVM testbench, which is well structured, documented, reusable, and easy to maintain. On-the-fly auto-validation ensures efficient and accurate code generation. You are left only with coding the required functions and checkers of any specific task, completely avoiding cumbersome codebase from the very start.
Acting as an Integrated Development Environment (IDE), Machina maintains a bug-free standard verification project structure, to avoid non-converging verification tasks surfacing towards design tapeout.
You can walk through the hierarchical structure of your project in a common file browser. Machina supports all three major simulators, while Machina invokes compilation and simulation tasks. Using Machina's built-in code editor, on-the-fly linting is performed, informing you of any syntax errors, so they can be fixed immediately rather than wait for the compilation process.
In Machina, DUT is connected to the UVM environment using smart GUI. You’ll be assisted by Machina’s auto-suggest connection scheme, and making it obsolete to manually connect hundreds of signals using files and coding.
As in all other Machina operations, DUT integration is fast, bypassing time consuming “copy-paste bugs”.
Functional coverage definition is also done using Machina’s simplified interface. This way, it can easily be reviewed by design teams, architects, and managers. Machina also automatically creates the SV coverage code, for 100% compliance with your definition. All team members who are familiar with the DUT functionality can readily define the coverage plan, avoiding non-synchronized coverage code and tedious UVM coverage coding.
Machina supports the entire spectrum of functional coverage options listed in IEEE Standard for SystemVerilog. Drop-down menus enable quick selection of coverage point type (simple or cross), bin type (simple, wildcard, ignore or illegal bin), all existing fields serving as samples, and any coverpoint that can be crossed.