An inspiring session connecting with future engineers 🤘

Łukasz Bielecki delivered a lecture on “Intro to Integrated Circuit Design”, walking through the full IC design landscape, from ASIC vs FPGA trade-offs and SoC architecture to the complete RTL to tape-out flow.

Michalina Kopcińska also shared her personal journey as a Junior Verification Engineer, along with practical advice on building the right skills and taking the first steps into the industry.

It’s always exciting to connect with the next generation of engineering talent 🚀

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