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Tips and Tricks
Verification Toolbox
Hands-On Debug Techniques, Workflow Hacks, and Professional Support
Xmodem protocol
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Verifying performance measurement counters in Verilog
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Testing interrupts extracted from file inside UVM sequence
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When using an array of UVCs, how can one tell which UVC sent an item to the scoreboard?
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What is the difference between shallow and deep copy?
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Why use non-blocking assignment in a driver?
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Xcelium: How to Enable Delta Events on Wave
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What can you do if you need to return two or more variables from a function?
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Vector bit-select and part-select addressing in SV using +: and -:
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Verilog Generate: Variable vs Signal Value
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Randomizing Fields of Register with Constraints
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Operator precedence and potential problems
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Printing UVM info inside properties/assertions
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RISC-V architecture: How to set up Control and Status Registers (CSRs) in order to enable counters
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Mounting LittleFS on Linux Machine
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Renaming files and replacing strings in them
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Randomization in C with NFSR logic
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Packing and unpacking data with uvm_packer.
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How to use “bind” to connect interfaces to modules in System Verilog?
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How to use code refactoring in DVT?
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IO connectivity table and testing
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Multiple Interface Instances
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How to verify the duration of any signal using SVA?
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Quickly navigate through your log
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How to start multiple instances of a single process in parallel using for/foreach loop?
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How to turn off or on assertion checking with system function?
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How to use Linux commands with SV/UVM – $system()
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How to use an argument from the command line to open a file?
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How to trace FreeRTOS based applications?
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How to show frequency of a signal in Simvision.
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How to print uvm_factory contents
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How to solve issues with time-consuming checkers in function?
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