Inspiring young engineers✨

Last Thursday, we visited the Silesian University of Technology in Gliwice to meet with second-year students from the Faculty of Electronics.

Dawid Zimończyk introduced students to the world of Verification Engineering, while Dominik Jurczyk shared his experience balancing studies and work at Vtool, along with practical advice for students interested in pursuing a career in verification.

Thank you to the university and students for the warm welcome — we are always excited to connect with future engineers!🤟

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