This paper explores how statistics and visualization, which remain largely unexploited today, can improve verification processes. Verification debug is data-intensive, and the biggest challenge for engineers is to grasp enormous amounts of data from different simulation outputs.

The growing complexity of SoCs is challenging the efficiency of present-day verification approaches, making verification processes increasingly more involved. As waveform databases expand in size and simulation run-time becomes more time consuming, logs and code execution traces are harder to read and understand. This requires greater resourcefulness from verification teams, alongside more powerful verification tools.

The verification of SoC hardware and software can present numerous challenges, with engineers dealing with the need to balance fast verification results and the inherent complexity of the system. This paper gives an overview of the flow that is followed in the SoC verification of the Ethernet Subsystem.

Debug often takes a large portion of the chip development and can significantly disrupt schedules.

How can we make debug more predictable and faster?

Vtool’s Cogita ^provides “an approach that combines machine learning with advanced visualization, and an all-inclusive debug methodology, that has been proven to reduce the debug cycle dramatically”, said Hagai Arbel, Vtool CEO.

Read all about ‘Debug: The Schedule Killer’ in this Semiconductor Engineering article by Brian Bailey.

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